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rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete 14-bit, 10 msps monolithic a/d converter ad9240 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781 ? analog devices, inc., functional block diagram vina capt capb sense otr bit 1 (msb) bit 14 (lsb) vref dvss avss ad9240 sha digital correction logic output buffers vinb 1v refcom 5 5 4 4 4 4 4 14 dvdd avdd clk mode select mdac3 gain = 8 mdac2 gain = 8 mdac1 gain = 16 a/d a/d a/d drvdd drvss cml bias a/d features monolithic 14-bit, 10 msps a/d converter low power dissipation: 285 mw single +5 v supply integral nonlinearity error: 2.5 lsb differential nonlinearity error: 0.6 lsb input referred noise: 0.36 lsb complete: on-chip sample-and-hold amplifier and voltage reference signal-to-noise and distortion ratio: 77.5 db spurious-free dynamic range: 90 db out-of-range indicator straight binary output data 44-lead mqfp product highlights the ad9240 offers a complete single-chip sampling 14-bit, analog-to-digital conversion function in a 44-lead metric quad flatpack. low power and single supply the ad9240 consumes only 280 mw on a single +5 v power supply. excellent dc performance over temperature the ad9240 provides no missing codes, and excellent tempera- ture drift performance over the full operating temperature range. excellent ac performance and low noise the ad9240 provides nearly 13 enob performance and has an input referred noise of 0.36 lsb rms. flexible analog input range the versatile onboard sample-and-hold (sha) can be configured for either single ended or differential inputs of varying input spans. flexible digital outputs the digital outputs can be configured to interface with +3 v and +5 v cmos logic families. excellent undersampling performance the full power bandwidth and dynamic range of the ad9240 make it well suited for direct-if down conversion extending to 45 mhz. product description the ad9240 is a 10 msps, single supply, 14-bit analog-to- digital converter (adc). it combines a low cost, high speed cmos process and a novel architecture to achieve the resolution and speed of existing hybrid implementations at a fraction of the power consumption and cost. it is a complete, monolithic adc with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. an external refer- ence can also be chosen to suit the dc accuracy and temperature drift requirements of the application. the device uses a multistage differential pipelined architecture with digital output error correc- tion logic to guarantee no missing codes over the full operating tempera ture range. the input of the ad9240 is highly flexible, allowing for easy interfacing to imaging, communications, medical and data- acquisition systems. a truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. the sample-and-hold amplifier (sha) is equally suited for multiplexed systems that switch full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the nyquist rate. the ad9240 also performs well in communication systems employ- ing direct-if down conversion, since the sha in the differen- tial input mode can achieve excellent dynamic performance well beyond its specified nyquist frequency of 5 mhz. a single clock input is used to control all internal conversion cycles. the digital output data is presented in straight binary output format. an out-of-range (otr) signal indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. b
rev. C2C ad9240Cspecifications dc specifications parameter ad9240 units resolution 14 bits min max conversion rate 10 mhz min input referred noise vref = 1 v 0.9 lsb rms typ vref = 2.5 v 0.36 lsb rms typ accuracy integral nonlinearity (inl) 2.5 lsb typ differential nonlinearity (dnl) 0.6 lsb typ 1.0 lsb max inl 1 2.5 lsb typ dnl 1 0.7 lsb typ no missing codes 14 bits guaranteed zero error (@ +25 c) 0.3 % fsr max gain error (@ +25 c) 2 1.5 % fsr max gain error (@ +25 c) 3 0.75 % fsr max temperature drift zero error 3.0 ppm/ c typ gain error 2 20.0 ppm/ c typ gain error 3 5.0 ppm/ c typ power supply rejection 0.1 % fsr max analog input input span (with vref = 1.0 v) 2 v p-p min input span (with vref = 2.5 v) 5 v p-p max input (vina or vinb) range 0 v min avdd v max input capacitance 16 pf typ internal voltage reference output voltage (1 v mode) 1 volts typ output voltage tolerance (1 v mode) 14 mv max output voltage (2.5 v mode) 2.5 volts typ output voltage tolerance (2.5 v mode) 35 mv max load regulation 4 5.0 mv max reference input resistance 5 kw typ power supplies supply voltages avdd +5 v ( 5% avdd operating) dvdd +5 v ( 5% dvdd operating) drvdd +5 v ( 5% drvdd operating) supply current iavdd 50 ma max (46 ma typ) idrvdd 1 ma max (0.1 ma typ) idvdd 15 ma max (11 ma typ) power consumption 330 mw max (285 mw typ) notes 1 vref = 1 v. 2 including internal reference. 3 excluding internal reference. 4 load regulation with 1 ma load current (in addition to that required by the ad9240). specification subject to change without notice. (avdd = +5 v, dvdd = +5 v, drvdd = +5 v, f sample = 10 msps, r bias = 2 k v , vref = 2.5 v, vinb = 2.5 v, t min to t max unless otherwise noted) b
ac specifications parameter ad9240 units signal-to-noise and distortion ratio (s/n+d) f input = 500 khz 75.0 db min 77.5 db typ f input = 1.0 mhz 77.5 db typ f input = 5.0 mhz 75.0 db typ effective number of bits (enob) f input = 500 khz 12.2 bits min 12.6 bits typ f input = 1.0 mhz 12.6 bits typ f input = 5.0 mhz 12.2 bits typ signal-to-noise ratio (snr) f input = 500 khz 76.0 db min 78.5 db typ f input = 1.0 mhz 78.5 db typ f input = 5.0 mhz 78.5 db typ total harmonic distortion (thd) f input = 500 khz C78.0 db max C85.0 db typ f input = 1.0 mhz C85.0 db typ f input = 5.0 mhz C77.0 db typ spurious free dynamic range f input = 500 khz 90.0 db typ f input = 1.0 mhz 90.0 db typ f input = 5.0 mhz 80.0 db typ dynamic performance full power bandwidth 70 mhz typ small signal bandwidth 70 mhz typ aperture delay 1 ns typ aperture jitter 4 ps rms typ acquisition to full-scale step (0.0025%) 45 ns typ overvoltage recovery time 167 ns typ specifications subject to change without notice. digital specifications parameters symbol ad9240 units clock input high level input voltage v ih +3.5 v min low level input voltage v il +1.0 v max high level input current (v in = dvdd) i ih 10 m a max low level input current (v in = 0 v) i il 10 m a max input capacitance c in 5 pf typ logic outputs (with drvdd = 5 v) high level output voltage (i oh = 50 m a) v oh +4.5 v min high level output voltage (i oh = 0.5 ma) v oh +2.4 v min low level output voltage (i ol = 1.6 ma) v ol +0.4 v max low level output voltage (i ol = 50 m a) v ol +0.1 v max output capacitance c out 5 pf typ logic outputs (with drvdd = 3 v) high level output voltage (i oh = 50 m a) v oh +2.4 v min low level output voltage (i ol = 50 m a) v ol +0.7 v max specifications subject to change without notice. ad9240 rev. C3C (avdd = +5 v, dvdd= +5 v, drvdd = +5 v, f sample = 10 msps, r bias = 2 k v , vref = 2.5 v, a in = C0.5 dbfs, ac coupled/differential input, t min to t max unless otherwise noted) (avdd = +5 v, dvdd = +5 v, t min to t max unless otherwise noted) b
ad9240 rev. C4C absolute maximum ratings* with respect parameter to min max units avdd avss C0.3 +6.5 v dvdd dvss C0.3 +6.5 v avss dvss C0.3 +0.3 v avdd dvdd C6.5 +6.5 v drvdd drvss C0.3 +6.5 v drvss avss C0.3 +0.3 v refcom avss C0.3 +0.3 v clk avss C0.3 avdd + 0.3 v digital outputs drvss C0.3 drvdd + 0.3 v vina, vinb avss C0.3 avdd + 0.3 v vref avss C0.3 avdd + 0.3 v sense avss C0.3 avdd + 0.3 v capb, capt avss C0.3 avdd + 0.3 v bias avss C0.3 avdd + 0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. switching specifications parameters symbol ad9240 units clock period 1 t c 100 ns min clock pulsewidth high t ch 45 ns min clock pulsewidth low t cl 45 ns min output delay t od 8n s m i n 13 ns typ 19 ns max pipeline delay (latency) 3 clock cycles notes 1 the clock period may be extended to 1 ms without degradation in specified performance @ +25 c. specifications subject to change without notice. (t min to t max with avdd = +5 v, dvdd = +5 v, drvdd = +5 v, r bias = 2 k v , c l = 20 pf) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9240 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. t cl t ch t c t od data 1 data output input clock analog input s1 s2 s3 s4 figure 1. timing diagram thermal characteristics thermal resistance 44-lead mqfp q ja = 53.2 c/w q jc = 19 c/w pin configuration 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 pin 1 identifier top view (not to scale) ad9240 12 13 14 15 16 17 18 19 20 21 22 nc = no connect bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 dvss avss dvdd avdd drvss drvdd clk nc nc nc (lsb) bit 14 refcom vref sense nc avss avdd nc nc otr bit 1 (msb) bit 2 nc nc nc cml nc capt capb bias nc vinb vina warning! esd sensitive device b
ad9240 rev. C5C overvoltage recovery time overvoltage recovery time is defined as that amount of time required for the adc to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converters range. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (+25 c) value to the value at t min or t max . power supply rejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d. aperture delay aperture delay is a measure of the sample-and-hold amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. signal-to-noise and distortion (s/n+d, sinad) ratio s/n+d is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the nyquist frequen cy, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the num- ber of bits. using the following formula, n = ( sinad C 1.76)/6.02 it is possible to get a measure of performance expressed as n , the effective number of bits. thus, an effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious free dynamic range (sfdr) sfdr is the difference in db between the rms amplitude of the input signal and the peak spurious signal. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. two-tone sfdr may be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale). pin function descriptions pin number name description 1 dvss digital ground 2, 29 avss analog ground 3 dvdd +5 v digital supply 4, 28 avdd +5 v analog supply 5 drvss digital output driver ground 6 drvdd digital output driver supply 7 clk clock input pin 8C10 nc no connect 11 bit 14 least significant data bit (lsb) 12C23 bit 13Cbit 2 data output bits 24 bit 1 most significant data bit (msb) 25 otr out of range 26, 27, 30 nc no connect 31 sense reference select 32 vref reference i/o 33 refcom reference common 34, 38, 40, 43, 44 nc no connect 35 bias* power/speed programming 36 capb noise reduction pin 37 capt noise reduction pin 39 cml common-mode level (midsupply) 41 vina analog input pin (+) 42 vinb analog input pin (C) *see speed/power programmability section. definitions of specification integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges. zero error the major carry transition should occur for an analog value 1/2 lsb below vina = vinb. zero error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. b
ad9240 rev. C6C typical differential ac characterization curves/plots (avdd = +5 v, dvdd = +5 v, drvdd = +5 v, f sample = 10 msps, r bias = 2 k v , t a = +25 8 c, differential input) input frequency C mhz 90 85 0.1 1 20 10 55 50 65 60 80 70 75 sinad C db C0.5dbfs C6.0dbfs C20.0dbfs figure 2. sinad vs. input frequency (input span = 5 v, v cm = 2.5 v) input frequency C mhz 90 85 0.1 1 20 10 55 50 65 60 80 70 75 sinad C db C0.5dbfs C6.0dbfs C20.0dbfs figure 5. si nad vs. input fre quency (input span = 2 v, v cm = 2.5 v) sample rate C mhz C60 C65 0.1 1 10 C95 C100 C85 C90 C70 C80 C75 thd C db 5v span 2v span figure 8. thd vs. sample rate (f in = 5.0 mhz, a in = C0.5 dbfs, v cm = 2.5 v) input frequency C mhz C40 C100 0.1 1 20 10 C90 C80 C70 C50 C60 thd C db C0.5dbfs C6.0dbfs C20.0dbfs figure 3. thd vs. input frequency (input span = 5 v, v cm = 2.5 v) input frequency C mhz C40 C100 0.1 1 20 10 C90 C80 C70 C50 C60 thd C db C20.0dbfs C6.0dbfs C0.5dbfs figure 6. thd vs. input frequency (input span = 2 v, v cm = 2.5 v) ain C db sfdr C dbc and dbfs 110 20 90 60 50 40 30 80 70 C60 C50 0 C40 C30 C20 C10 5v span C dbc 2v span C dbfs 5v span C dbfs 100 2v span C dbc figure 9. single tone sfdr (f in = 5.0 mhz, v cm = 2.5 v) frequency C mhz amplitude C db 0 C70 C100 0 5.0 C10 C60 C80 C90 C40 C50 C20 C30 C110 C120 1st 9th 8th 2nd 3rd 7th 6th 4th 5th figure 4. typical fft, f in = 1.0 mhz (input span = 5 v, v cm = 2.5 v) 2 frequency C mhz amplitude C db 0 C15 C30 C45 C60 C75 C90 C105 C120 C135 C150 1 3 4 5 6 7 8 9 0 5.0 figure 7. typical fft, f in = 5.0 mhz (input span = 2 v, v cm = 2.5 v) input power level ( f 1 = f 2 ) C dbfs worst case spurious C dbc and dbfs 110 60 C40 C35 0 C30 C25 C20 C15 C10 C5 105 90 85 75 65 100 95 80 70 5v span C dbfs 5v span C dbc 2v span C dbfs 2v span C dbc figure 10. dual tone sfdr (f 1 = 0.95 mhz, f 2 = 1.04 mhz, v cm = 2.5 v) b
ad9240 rev. C7C other characterization curves/plots (avdd = +5 v, dvdd = +5 v, drvdd = +5 v, f sample = 10 msps, r bias = 2 k v , t a = +25 8 c, single-ended input) code inl C lsb 3.0 C0.5 C2.0 0 16863 2.5 0.0 C1.0 C1.5 2.0 1.0 1.5 0.5 C2.5 C3.0 figure 11. typical inl (input span = 5 v) input frequency C mhz 90 85 40 0.1 1 20 10 55 45 50 65 60 80 70 75 sinad C db C0.5dbfs C6.0dbfs C20.0dbfs figure 14. si nad vs. input fre quency (input span = 2 v, v cm = 2.5 v) input frequency C mhz 90 85 0.1 1 20 10 55 50 65 60 80 70 75 sinad C db C0.5dbfs C6.0dbfs C20.0dbfs figure 17. sinad vs. input fre quency (input span = 5 v, v cm = 2.5 v) code dnl C lsb 1.0 C0.4 C1.0 0 16383 0.8 C0.2 C0.6 C0.8 0.6 0.2 0.4 0.0 figure 12. typical dnl (input span = 5 v) input frequency C mhz C40 C100 0.1 1 20 10 C90 C80 C70 C50 C60 thd C db C0.5dbfs C6.0dbfs C20.0dbfs figure 15. thd vs. input frequency (input span = 2 v, v cm = 2.5 v) input frequency C mhz C40 C100 0.1 1 20 10 C90 C80 C70 C50 C60 thd C db C0.5dbfs C6.0dbfs C20dbfs figure 18. thd vs. input frequency (input span = 5 v, v cm = 2.5 v) nC1 13484335 1414263 1482053 n n+1 hits code figure 13. grounded-input histogram (input span = 5 v) frequency C mhz 0 C10 1 10 100 C70 C80 C50 C60 C20 C40 C30 amplitude C db figure 16. cmr vs. input fre quency (input span = 2 v, v cm = 2.5 v) temperature C 8c v ref error C v 0.01 C0.004 C0.01 C60 C40 140 C20 0 20 40 60 80 100 120 0.008 C0.002 C0.006 C0.008 0.002 0 0.006 0.004 figure 19. typical voltage reference error vs. temperature b
ad9240 rev. C8C clock frequency C mhz sinad C db 80 20 12 0 10 70 60 50 40 30 10 0 r bias = 10kv r bias = 20kv r bias = 200kv r bias = 4kv r bias = 2kv figure 21. sinad vs. clock frequency for varying r bias values (v cm = 2.5 v, a in = C0.5 db, 5 v span, f in = f clk /2) clock frequency C mhz power C mw 400 100 220 4 6 8 10 12 14 16 18 350 300 250 200 150 r bias = 1.7kv r bias = 2kv r bias = 2.5kv r bias = 3.3kv r bias = 5kv r bias = 10kv r bias = 100k v figure 22. power dissipation vs. clock frequency for varying r bias values analog input and reference overview figure 23, a simplified model of the ad9240, highlights the rela- tionship between the analog inputs, vina, vinb, and the ref- erence voltage, vref. like the voltage applied to the top of the resistor ladder in a flash a/d converter, the value vref defines the maximum input voltage to the a/d core. the minimum input voltage to the a/d core is automatically defined to be Cvref. v core vina vinb +vref Cvref a/d core 14 ad9240 figure 23. equivalent functional input circuit introduction the ad9240 uses a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (sha) implemented on a cost-effective cmos process. each stage of the pipeline, excluding the last, consists of a low resolution flash a/d con- nected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier amplifies the differ- ence between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each of the stages to facilitate digital correction of flash er- rors. the last stage simply consists of a flash a/d. the pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. this means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. this latency is not a concern in most applications. the digital output, together with the out-of-range indicator (otr), is latched into an output buffer to drive the output pins. the output drivers can be con- figured to interface with +5 v or +3.3 v logic families. the ad9240 uses both edges of the clock in its internal timing circuitry (see figure 1 and specification page for exact timing requirements). the a/d samples the analog input on the rising edge of the clock input. during the clock low time (between the falling edge and rising edge of the clock), the input sha is in the sample mode; during the clock high time it is in the hold mode. system disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input sha to acquire the wrong value, and should be minimized. speed/power programmability the ad9240s maximum conversion rate and associated power dissipation can be set using the parts bias pin. a simplified diagram of the on-chip circuitry associated with the bias pin is shown in figure 20. ad9240 bias r bias i f ixed adc bias figure 20. the value of r bias can be varied over a limited range to set the maximum sample rate and power dissipation of the ad9240. a typical plot of s/(n+d) @ f in = nyquist vs. f clk at varying r bias is shown in figure 21. a similar plot of power vs. f clk at varying r bias is shown in figure 22. these plots indicate typical performance vs. r bias . note that all other plots and specifications in this data sheet reflect performance at a fixed r bias = 2 k w . b
ad9240 rev. C9C the addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. the input stage allows the user to easily con- figure the inputs for either single-ended operation or differential operation. the a/ds input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. specifically, the input to the a/d core is the differ- ence of the voltages applied at the vina and vinb input pins. therefore, the equation, v core = vina C vinb (1) defines the output of the differential input stage and provides the input to the a/d core. the voltage, v core , must satisfy the condition, C vref v core vref (2) where vref is the voltage at the vref pin. while an infinite combination of vina and vinb inputs exist that satisfy equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the ad9240. the power supplies bound the valid operating range for vina and vinb. the condition, avss C 0.3 v < vina < avdd + 0.3 v (3) avss C 0.3 v < vinb < avdd + 0.3 v where avss is nominally 0 v and avdd is nominally +5 v, defi nes this requirement. thus, the range of valid inputs for vina and vinb is any combination that satisfies both equa- tions 2 and 3. for additional information showing the relationship between vina, vinb, vref and the digital output of the ad9240, see table iv. refer to table i and table ii for a summary of the various analog input and reference configurations . analog input operation figure 24 shows the equivalent analog input of the ad9240 which consists of a differential sample -and-hold amplifier (sha). the differential input structure of the sha is highly flexible, allowing the devices to be easily configured for either a differen- tial or single-ended input. the dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single- supply or dual supply systems. note also that the analog inputs, vina and vinb, are interchangeable with the exception that reversing the inputs to the vina and vinb pins results in a polarity inversion. vina vinb c pin + c par c pin C c par q s1 q s1 q h1 c s c s c h c h q s2 q s2 figure 24. simplified input circuit the input sha of the ad9240 is optimized to meet the perfor- mance requirements for some of the most demanding commu- nication, imaging, and data acquisition applications while maintaining low power dissipation. figure 25 is a graph of the full-power bandwidth of the ad9240, typically 60 mhz. note that the small signal bandwidth is the same as the full-power bandwidth. the settling time response to a full-scale stepped input is shown in figure 26 and is typically less than 40 ns to 0.0025%. the low input referred noise of 0.36 lsbs rms is displayed via a grounded histogram and is shown in figure 13. frequency C mhz 1 0 C7 1 10 100 C3 C4 C5 C6 C1 C2 C8 C9 C10 amplitude C db figure 25. full-power bandwidth settling time C ns code 16000 12000 0 0 60 10 20 30 40 50 8000 4000 70 80 figure 26. settling time the shas optimum distortion performance for a differential or single-ended input is achieved under the following two condi- tions: (1) the common-mode voltage is centered around mid- supply (i.e., avdd/2 or approximately 2.5 v) and (2) the input signal voltage span of the sha is set at its lowest (i.e., 2 v input span). this is due to the sampling switches, q s1 , being cmos switches whose r on resistance is very low but has some signal dependency which causes frequency dependent ac distortion while the sha is in the track mode. the r on resistance of a cmos switch is typically lowest at its midsupply but increases symmetrically as the input signal approaches either avdd or avss. a lower input signal voltage span centered at midsupply reduces the degree of r on modulation. b
ad9240 rev. C10C figure 27 compares the ad9240s thd vs. frequency perfor- mance for a 2 v input span with a common- mode voltage of 1 v and 2.5 v. note the difference in the amount of degrada- tion in thd performance as the input frequency increases. similarly, note how the thd performance at lower frequencies becomes less sensitive to the common-mode voltage. as the input frequency approaches dc, the distortion will be domi- nated by static nonlinearities such as inl and dnl. it is important to note that these dc static nonlinearities are inde- pendent of any r on modulation. C50 C80 0.1 1 20 C70 C60 C90 10 thd C db frequency C mhz v cm = 1.0v v cm = 2.5v figure 27. thd vs. frequency for v cm = 2.5 v and 1.0 v (a in = C0.5 db, input span = 2.0 v p-p) due to the high degree of symmetry within the sha topology, a significant improvement in distortion performance for differen- tial input signals with frequencies up to and beyond nyquist can be realized. this inherent symmetry provides excellent cancella- tion of both common-mode distortion and noise. also, the required input signal voltage span is reduced a factor of two which further reduces the degree of r on modulation and its effects on distortion. the optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 v input span) and matched input impedance for vina and vinb. note that only a slight degradation in dc linearity performance exists between the 2 v and 5 v input span as specified in the ad9240 dc specifications. referring to figure 24, the differential sha is implemented using a switched-capacitor topology. hence, its input imped- ance and its subsequent effects on the input drive source should be understood to maximize the converters performance. the combination of the pin capacitance, c pin , parasitic capacitance c par, and the sampling capacitance, c s , is typically less than 16 pf. when the sha goes into track mode, the input source must charge or discharge the voltage stored on c s to the new input voltage. this action of charging and discharging c s which is approximately 4 pf, averaged over a period of time and for a given sampling frequency, f s , makes the input impedance ap- pear to have a benign resistive component (i.e., 83 k w at f s = 10 msps). however, if this action is analyzed within a sam- pling period (i.e., t = <1/f s ), the input impedance is dynamic due to the instantaneous requirement of charging and discharg- ing c s . a series resistor inserted between the input drive source and the sha input as shown in figure 28 provides effective isolation. 10mf vina vinb sense ad9240 0.1mf r s * v cc v ee r s * vref refcom *optional series resistor figure 28. series resistor isolates switched-capacitor sha input from op amp. matching resistors improve snr performance the optimum size of this resistor is dependent on several fac- tors, which include the ad9240 sampling rate, the selected op amp and the particular application. in most applications, a 30 w to 50 w resistor is sufficient; however, some applications may require a larger resistor value to reduce the noise band- width or possibly limit the fault current in an overvoltage condition. other applications may require a larger resistor value as part of an antialiasing filter. in any case, since the thd performance is dependent on the series resistance and the above mentioned factors, optimizing this resistor value for a given application is encouraged. a slight improvement in snr performance and dc offset performance is achieved by matching the input resistance con- nected to vina and vinb. the degree of improvement is de- pendent on the resistor value and the sampling rate. for series resistor values greater than 100 w , the use of a matching resis- tor is encouraged. the noise or small-signal bandwidth of the ad9240 is the same as its full-power bandwidth. for noise sensitive applications, the excessive bandwidth may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wide- band noise at the a/ds input by forming a low-pass filter. note, however, that the combination of this series resistance with the equivalent input capacitance of the ad9240 should be evalu- ated for those time-domain applications that are sensitive to the input signals absolute settling time. in applications where har- monic distortion is not a primary concern, the series resistance may be selected in combination with the shas nominal 16 pf of input capacitance to set the filters 3 db cutoff frequency. a better method of reducing the noise bandwidth, while possi- bly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., vina and/or vinb) and analog ground. since this additional shunt capacitance combines with the equivalent input capaci- tance of the ad9240, a lower series resistance can be selected to establish the filters cutoff frequency while not degrading the distortion performance of the device. the shunt capacitance also acts as a charge reservoir, sinking or sourcing the additional charge required by the hold capacitor, c h , further reducing current transients seen at the op amps output. the effect of this increased capacitive load on the op amp driv- ing the ad9240 should be evaluated. to optimize performance when noise is the primary consideration, increase the shunt capacitance as much as the transient response of the input signal will allow. increasing the capacitance too much may adversely affect the op amps settling time, frequency response and distor- tion performance. b
ad9240 rev. C11C table i. analog input configuration summary input input input range (v) figure connection coupling span (v) vina 1 vinb 1 # comments single-ended dc 2 0 to 2 1 32, 33 best for stepped input response applications, suboptimum thd and noise performance, requires 5 v op amp. 2 vref 0 to vref 32, 33 same as above but with improved noise performance due to 2 vref increase in dynamic range. headroom/settling time requirements of 5 v op amp should be evaluated. 5 0 to 5 2.5 32, 33 opti mum noise performance, excellent thd performance. requires op amp with vcc > +5 v due to insufficient headroom @ 5 v. 2 vref 2.5 C vref 2.5 39 optimum thd performance with vref = 1, noise performance to improves while thd performance degrades as vref increases 2.5 + vref to 2.5 v. single s upply operation (i.e., +5 v) for many op amps. single-ended ac 2 or 0 to 1 or 1 or vref 34 suboptimum ac performance due to input common-mode level 2 vref 0 to 2 vref not biased at optimum midsupply level (i.e., 2.5 v). 5 0 to 5 2.5 34 optimum noise performance, excellent thd performance. 2 vref 2.5 C vref 2.5 35 flexible input range, optimum thd performance with vref = 1. to noise performance improves while thd performance degrades as 2.5 + vref vref increases to 2.5 v. differential ac or 2 2 to 3 3 to 2 29C31 optimum full-scale thd and sfdr performance well beyond the dc a/ds nyquist frequency. 2 vref 2.5 C vref/2 2.5 + vref/2 29C31 same as 2 v to 3 v input range with the exception that full-scale to to thd and sfdr performance can be traded off for better noise 2.5 + vref/2 2.5 C vref/2 performance. 5 1.25 to 3.75 3.75 to 1.25 29C31 widest dynamic range (i.e., enobs) due to optimum noise performance. 1 vina and vinb can be interchanged if signal inversion is required. table ii. reference configuration summary reference input span (vinaCvinb) operating mode (v p-p) required vref (v) connect to internal 2 1 sense vref internal 5 2.5 sense refcom internal 2 span 5 and 1 vref 2.5 and r1 vref and sense span = 2 vref vref = (1 + r1/r2) r2 sense and refcom external 2 span 51 vref 2.5 sense avdd (nondynamic) vref ext. ref. external 2 span 5 capt and capb sense avdd (dynamic) externally driven vref refcom ext. ref. 1 capt ext. ref. 2 capb b
ad9240 rev. C12C reference operation the ad9240 contains an onboard bandgap reference that pro- vides a pin-strappable option to generate either a 1 v or 2.5 v output. with the addition of two external re sistors, the user can generate reference voltages other than 1 v and 2.5 v. another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. see table ii for a summary of the pin-strapping options for the ad9240 reference configurations. figure 29 shows a simplified model of the internal voltage reference of the ad9240. a pin-strappable reference ampli- fier buffers a 1 v fixed reference. the output from the refer- ence amplifier, a1, appears on the vref pin. the voltage on the vref pin determines the full-scale input span of the a/d. this input span equals, full-scale input span = 2 vref the voltage appearing at the vref pin as well as the state of the internal reference amplifier, a1, are determined by the volt- age appearing at the sense pin. the logic circuitry contains two comparators which monitor the voltage at the sense pin. the comparator with the lowest set point (approximately 0.3 v) controls the position of the switch within the feedback path of a1. if the sense pin is tied to refcom, the switch is con- nected to the internal resistor network thus providing a vref of 2.5 v. if the sense pin is tied to the vref pin via a short or resistor, the switch is connected to the sense pin. a short will provide a vref of 1.0 v while an external resistor network will provide an alternative vref between 1.0 v and 2.5 v. the second comparator controls internal circuitry that will disable the reference amplifier if the sense pin is tied avdd. disabling the reference amplifier allows the vref pin to be driven by an external voltage reference. a2 5kv 5kv 5kv 5kv logic disable a2 7.5kv logic a1 5kv disable a1 1v to a/d ad9240 capt capb vref sense refcom figure 29. equivalent reference circuit the actual reference voltages used by the internal circuitry of the ad9240 appear on the capt and capb pins. for proper operation when using the internal or an external reference, it is necessary to add a capacitor network to decouple these pins. figure 30 shows the recommended decoupling network. this capacitive network performs the following three functions: (1) along with the reference amplifier, a2, it provides a low source impedance over a large frequency range to drive the a/d inter- nal circuitry, (2) it provides the necessary compensation for a2 and (3) it bandlimits the noise contribution from the reference. the turn-on time of the reference voltage appearing between capt and capb is approximately 15 ms and should be evalu- ated in any power-down mode of operation. 0.1mf 10mf 0.1mf 0.1mf capt capb ad9240 figure 30. r ecommended capt/capb decoupling network the a/ds input span may be varied dynamically by changing the differential reference voltage appearing across capt and capb symmetrically around 2.5 v (i.e., midsupply). to change the reference at speeds beyond the capabilities of a2, it will be necessary to drive capt and capb with two high speed, low noise amplifiers. in this case, both internal amp lifiers (i.e., a1 and a2) must be disabled by connecting sense to avdd and vref to refcom and the capacitive decoupling network removed. the external voltages applied to capt and capb must be 2.5 v + input span/4 and 2.5 v C input span/4, respec- tively, where the input span can be varied between 2 v and 5 v. note that those samples within the pipeline a/d during any reference transition will be corrupted and should be discarded. b
ad9240 rev. C13C driving the analog inputs introduction the ad9240 has a highly flexible input structure allowing it to interface with single-ended or differential input interface cir- cuitry. the applications shown in sections driving the analog inputs and reference configurations, along with the informa- tion presented in the input and reference overview section of this data sheet, give examples of both single-ended and differen- tial operation. refer to tables i and ii for a list of the different possible input and reference configurations and their associated figures in the data sheet. the optimum mode of operation, analog input range and asso- ciated interface circuitry will be determined by the particular applications performance requirements as well as power supply options. for example, a dc coupled single-ended input may be appropriate for many data acquisition and imaging applications. also, many communication applications which require a dc coupled input for proper demodulation can take advantage of the ex cellent single-ended distortion performance of the ad9240. the input span should be configured such that the systems performance objectives and the headr oom requirements of the driving op amp are simultaneously met. alternatively, the differential mode of operation provides the best thd and sfdr performance over a wide frequency range. a transformer coupled differential input should be considered for the most demanding spectral-based applications which allow ac coupling (e.g., direct if to digital conversion). the dc- coupled d ifferential mode of operation also provides an enhance- ment in distortion and noise performance at higher input spans. furthermore, it allows the ad9240 to be configured for a 5 v span using op amps specified for +5 v or 5 v operation. single-ended operation requires that vina be ac or dc coupled to the input signal source while vinb of the ad9240 be biased to the appropriate voltage corresponding to a midscale code transition. note that signal inversion may be easily accom- plished by transposing vina and vinb. differential operation requires that vina and vinb be simulta- neously driven with two equal signals that are in and out of phase versions of the input signal. differential operation of the ad9240 offers the following benefits: (1) signal swings are smaller and therefore linearity requirements placed on the input signal source may be easier to achieve, (2) signal swings are smaller and therefore may allow the use of op amps which may otherwise have been constrained by headroom limitations, (3) differential operation minimizes even-order harmonic prod- ucts and (4) differential operation offers noise immunity based on the devices common-mode rejection as shown in figure 16. as is typical of most cmos devices, exceeding the supply limits will turn on internal parasitic diodes resulting in transient cur- rents within the device. figure 31 shows a simple means of clamping a dc coupled input with the addition of two series resistors and two diodes. note that a larger series resistor could be used to limit the fault current through d1 and d2 but should be evaluated since it can cause a degradation in overall performance. avdd r s1 30v v cc v ee d2 1n4148 d1 1n4148 r s2 20v ad9240 figure 31. simple clamping circuit differential mode of operation since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. a single-ended-to- differential conversion can be realized with an rf transformer or a dual op amp differential driver. the optimum method depends on whether the application requires the input signal to be ac or dc coupled to ad9240. ac coupling via an rf transformer an rf transformer with a center tap can be used to generate differential inputs for the ad9240. it provides all of the benefits of operating the adc in the differential mode while cont ribut- ing no additional noise and minimal distortion. as a result, an rf transformer is recommended in high frequency applica- tions, especially undersampling, in which the performance of a dual op amp differential driver may not be adequ ate. an rf transformer has the added benefit of providing electrical isola- tion between the signal source and the adc. however, since the lower cutoff frequency of most rf transformers is nominally a few 100 khz, a dual op amp differential driver may be more suit- able in ac-coup ling applications, where the spectral content of the input signal falls below the cutoff frequency of a suitable rf transformer. figure 32 is a suggested transformer circuit using a mini- circuits rf transformer, model #t4-6t, which has an imped- ance ratio of four (turns ratio of 2). the 1:4 impedance ratio requires the 200 w secondary termination for optimum power transfer and vswr. the centertap of the transformer provides a convenient means of level-shifting the input signal to a de- sired common-mode voltage. optimum performance can be realized when the centertap is tied to cml of the ad9240 which is the common-mode bias level of the internal sha. vina cml vinb ad9240 0.1mf 200v mini-circuits t4-6t 50v figure 32. transformer coupled input transformers with other turns ratios may also be selected to optimize the performance of a given application. for example, a given input signal source or amplifier may realize an improve- ment in distortion performance at reduced output power levels and signal swings. hence, selecting a transformer with a higher impedance ratio (i.e., mini-circuits t16-6t with a 1:16 imped- ance ratio) effectively steps up the signal level, further reduc- ing the driving requirements of the signal source. b
ad9240 rev. C14C ac coupling with op amps as previously stated, a dual op amp differential driver may be more suitable in applications in which the spectral content of the input signal falls below the cutoff frequency of a suitable rf transformer and/or the cost of an rf transformer and a low distortion driver for the transformer is prohibitive. the ac-coupled differential driver shown in figure 33 is best suited for 5 v systems in which the input signal is ground referenced. in this case, v cm will be 0 v. this driver circuit can achieve performance similar to an rf transformer over the ad9240s full nyquist bandwidth of 5 mhz. however, unlike the rf transformer, the lower cutoff frequency can be arbitrarily set low by adjusting the rc time constant formed by c c and r b /2. c n , in combination with r s , can be used to limit the con- tribution of op amp-generated noise at higher frequencies. low cost, high performance dual op amps operating from 5 v such as the ad8056 and ad8058, are excellent choices for this appli- cation and are capable of maintaining 78 db snr and 83 db thd at 1 mhz (5 v span). an optional resistor r o can be added to u1b to achieve a similar group delay as u1a, potentially improving overall distortion performance. a resistor divider net- work formed by r b centers the in puts of the ad9240 around avdd/2 to achieve its optimum distortion performance. v cm source r o c n r b 5kv r s c c 0.1mf v cc r b 5kv c c 0.1mf v cc u1a u1b r s r b 5kv r b 5kv figure 33. ac coupling of op amps dc coupling with op amps the dc-coupled differential driver in figure 34 is best suited for 5 v systems in which the input signal is ground referenced and optimum distortion performance is desired. this driver circuit provides the ability to level-shift the input signal to within the common-mode range of the ad9240. the two op amps are configured as matched differential amps with the input signal applied to opposing inputs to provide the differential output. the common-mode offset voltage is applied to the noninverting resistor n etwork, which provides the proper level shifting. the ad9631 is given as the amplifier of choice in this application due to its s uperior distortion performance for relatively large output sw ings and wide bandwidth. if cost or space are factors, the ad8056 dual op amp will save on both, but at the cost of slightly increased distortion with large signal levels. figure 34 also illustrates the use of protection diodes, which are used to protect the ad9240 from any fault condition in which the op amps outputs inadvertently go above v dd or below gnd. vina vinb cml ad9240 390v 390v v in v cml Cvin v cml +vin avdd 390v 390v 220v 390v avdd 390v 220v 390v ad9631 ad9631 2.5kv 33v 100v 0.1mf 1mf 0.1mf op113 33v 390v 0.1mf 0.1mf figure 34. differential driver with level-shifting single supply dc-coupled driver the circuit of figure 33 can be easily modified for a single supply, dc-coupled application. this is done by biasing v cm to avdd/2, the normal common-mode level in a single supply system. since the outputs of the op amps are centered at avdd/2, the ac coupling network of c c and r b can be removed. with this done, the differential driving pair can now be run from a single supply. single-ended mode of operation the ad9240 can be configured for single-ended operation using dc or ac coupling. in either case, the input of the a/d must be driven from an operational amplifier that will not de- grade the a/ds performance. because the a/d operates from a single supply, it will be necessary to level-shift ground-based bipolar signals to comply with its input requirements. both dc and ac coupling provide this necessary function, but each method re sults in different interface issues which may influence the system design and performance. dc coupling and interface issues many applications require the analog input signal to be dc coupled to the ad9240. an operational amplifier can be con- figured to rescale and level-shift the input signal so it is compat- ible with the selected input range of the a/d. the input range to the a/d should be selected on the basis of system perfor- mance objectives as well as the analog power supply availability since this will place certain constraints on the op amp selection. many of the new high performance op amps are specified for only 5 v operation and have limited input/output swing capa- bilities. hence, the selected input range of the ad9240 should be sensitive to the headroom requirements of the particular op amp to prevent clipping of the signal. also, since the output of a dual supply amplifier can swing below C0.3 v, clamping its output should be considered in some applications. in some applications, it may be advantageous to use an op amp specified for single supply +5 v operation since it will inherently limit its output swing to within the power supply rails. rail-to- rail output amplifiers such as the ad8041 allow the ad9240 to be configured with larger input spans which improves the noise performance. b
ad9240 rev. C15C if the application requires the largest single-ended input range (i.e., 0 v to 5 v) of the ad9240, the op amp will require larger supplies to drive it. various high speed amplifiers in the op amp selection guide of this data sheet can be selected to accommodate a wide range of supply options. once again, clamping the output of the amplifier should be considered for these applications. alternatively, a single-ended to differential op amp driver circuit using the ad8042 could be used to achieve the 5 v input span while operating from a single +5 v supply as discussed in the previous section. two dc coupled op amp circuits using a noninverting and inverting top ology are discussed below. although not shown, the noninverting and inverting topologies can be easily config- ured as part of an antialiasing filter by using a sallen-key or multiple-feedback topology, respectively. an additional r-c network can be inserted between the op amps output and the ad9240 input to provide a real pole. simple op amp buffer in the simplest case, the input signal to the ad9240 will already be biased at levels in accordance with the selected input range. it is simply necessary to provide an adequately low source im- pedance for the vina and vinb analog input pins of the a/d. figure 35 shows the recommended configuration for a single- ended drive using an op amp. in this case, the op amp is shown in a noninverting unity gain configuration driving the vina pin. the internal reference drives the vinb pin. note that the addi- tion of a small series resistor of 30 w to 50 w connected to vina and vinb will be beneficial in nearly all cases. refer to the analog input operation section for a discussion on resistor selection. figure 35 shows the proper connection for a 0 v to 5 v input range. alternative single ended input ranges of 0 v to 2 vref can also be realized with the proper configuration of vref (refer to the section, using the internal reference). 10mf vina vinb sense ad9240 0.1mf r s +v Cv r s vref 5v 0v u1 2.5v figure 35. single-ended ad9240 op amp drive circuit op amp with dc level-shifting figure 36 shows a dc-coupled level-shifting circuit employing an op amp, a1, to sum the input signal with the desired dc offset. configuring the op amp in the inverting mode with the given resistor values results in an ac signal gain of C1. if the signal inversion is undesirable, interchange the vina and vinb con- nections to reestablish the original signal polarity. the dc volt- age at vref sets the common-m ode voltage of the ad9240. for example, when vref = 2.5 v, the output level from the op amp will also be centered around 2.5 v. the use of ratio matched, thin-film resistor networks will minimize gain and offset errors. an optional pull-up resistor, r p , may also be used to reduce the output load on vref to 1 ma. 0v dc +vref Cvref vina vinb ad9240 0.1mf 500v* 0.1mf 500v* a1 nc nc +v cc 500v* r s vref 500v* r s r p ** avdd *optional resistor network-ohmtek orna500d **optional pull-up resistor when using internal reference figure 36. si ngle-ended input with dc-coupled level-shift ac coupling and interface issues for applications where ac coupling is appropriate, the op amps output can be easily level-shifted to the common-mode voltage, v cm , of the ad9240 via a coupling capacitor. this has the advantage of allowing the op amps common-mode level to be symmetrically biased to its midsupply level (i.e., (v cc + v ee )/ 2). op amps that operate symmetrically with respect to their power supplies typically provide the best ac performance as well as greatest input/output span. hence, various high speed/ performance amplifiers that are restricted to +5 v/C5 v op- eration and/or specified for +5 v single-supply operation can be easily configured for the 5 v or 2 v input span of the ad9240, respectively. the best ac distortion performance is achieved when the a/d is configured for a 2 v input span and common- mode voltage of 2.5 v. note that differential transformer coupling, which is another form of ac coupling, should be considered for optimum ac performance. simple ac interface figure 37 shows a typical example of an ac-coupled, single- ended configuration. the bias voltage shifts the bipolar, ground-referenced input signal to approximately vref. the value for c1 and c2 will depend on the size of the resistor, r. the capacitors, c1 and c2, are typically a 0.1 m f ceramic and 10 m f tantalum capacitor in parallel to achieve a low cutoff frequency while main taining a low impedance over a wide fre- quency range. the com bination of the capacitor and the resistor form a high-pass filter with a high-pass C3 db frequency deter- mined by the equation, f C3 db = 1/(2 p r ( c 1 + c 2)) c2 vina vinb sense ad9240 c1 r +5v C5v r s vref +vref 0v Cvref v in c2 c1 r s figure 37. ac-coupled input the low impedance vref voltage source biases both the vinb input and provides the bias voltage for the vina input. figure 37 shows the vref configured for 2.5 v. thus the input range of the a/d is 0 v to 5 v. other input ranges could be selected by changing vref but the a/ds distortion performance will b
ad9240 rev. C16C degrade slightly as the input common-mode voltage deviates from its optimum level of 2.5 v. alternative ac interface figure 38 shows a flexible ac-coupled circuit which can be con- figured for different input spans. since the common-mode voltage of vina and vinb are biased to midsupply indepen- dent of vref, vref can be pin-strapped or reconfigured to achieve input spans between 2 v and 5 v p-p. the ad9240s cmrr along with the symmetrical coupling r-c networks will reject both power supply variations and noise. the resistors, r, establish the common-mode voltage. they may have a high value (e.g., 5 k w ) to minimize power consumption and establish a low cutoff frequency. the capacitors, c1 and c2, are typically a 0.1 m f ceramic and 10 m f tantalum capacitor in parallel to achieve a low cutoff frequency while maintaining a low imped- ance over a wide frequency range. r s isolates the buffer ampli- fier from the a/d input. the optimum performance is achieved when vina and vinb are driven via symmetrical networks. the high pass f C3 db point can be approximated by the equation, f C3 db = 1/(2 p r /2 ( c 1 + c 2)) c2 vina vinb ad9240 c1 r +5v C5v r s v in c1 c2 r r s +5v r r +5v figure 38. ac -coupled input-flexible input span, v cm = 2.5 v op amp selection guide op amp selection for the ad9240 is highly dependent on a particular application. in general, the performance requirements of any given application can be characterized by either time domain or frequency domain parameters. in either case, one should carefully select an op amp that preserves the perfor- mance of the a/d. this task becomes challenging when one considers the ad9240s high performance capabilities coupled with other external system level requirements such as power consumption and cost. the ability to select the optimal op amp may be further compli- cated by limited power supply availability and/or limited accept- able supplies for a desi red op amp. newer, high performance op amps typically have i nput and output range limitations in accor- dance with their lower supply voltages. as a result, some op amps will be more appropriate in systems where ac-coupling is allow able. when dc-coupling is required, op amps without headroom constraints such as rail-to-rail op amps or ones where larger supplies can be used should be considered. the following section describes some op amps currently available from analog devices. the system designer is always encouraged to contact the factory or local sales office to be updated on analog de- vices latest amplifier product offerings. highlights of the areas where the op amps excel and where they may limit the perfor- mance of the ad9240 are also included. ad9631: 220 mhz unity gbw, 16 ns settling to 0.01%, 5 v supplies best applications: best ac specs, low noise, ac-coupled limits: usable input/output range, power consumption ad8047: 130 mhz unity gbw, 30 ns settling to 0.01%, 5 v supplies best applications: good ac specs, low noise, ac-coupled limits: thd > 5 mhz, usable input range ad8042: dual ad8041 best applications: differential and/or low imped- ance input drivers limits: noise with 2 v input range reference configurations for the purpose of simplicity, the figures associated with this section on internal and external reference operation do not show recommended matching series resistors for vina and vinb. please refer to section driving the analog inputs, intro- duction, for a discussion of this topic. the figures do not show the decoupling network associated with the capt and capb pins. please refer to the reference o peration section for a discus- sion of the internal reference circuitry and the recommended decoupling network shown in figure 30. using the internal reference single-ended input with 0 to 2 3 vref range figure 39 shows how to connect the ad9240 for a 0 v to 2 v or 0 v to 5 v input range via pin strapping the sense pin. an intermediate input range of 0 to 2 vref can be established using the resistor programmable configuration in figure 41 and connecting vref to vinb. 10mf vina vref ad9240 0.1mf vinb 2xvref 0v short for 0 to 2v input span sense short for 0 to 5v input span refcom figure 39. internal reference (2 v p-p input span, v cm = 1 v, or 5 v p-p input span, v cm = 2.5 v) in either case, both the common-mode voltage and input span are directly dependent on the value of vref. more specifically, the common-mode voltage is equal to vref while the input span is equal to 2 vref. thus, the valid input range extends from 0 to 2 vref. when vina is 0 v, the digital output will be 0000 hex; when vina is 3 2 vref, the digital output will be 3fff hex. shorting the vref pin directly to the sense pin places the internal reference amplifier in unity-gain mode and the result- ant vref output is 1 v. the valid input range is, therefore, 0 v to 2 v. shorting the sense pin directly to the refcom pin configures the internal reference amplifier for a gain of 2.5 and b
ad9240 rev. C17C the resultant vref output is 2.5 v. the valid input range thus becomes 0 v to 5 v. the vref pin should be bypassed to the refcom pin with a 10 m f tantalum capacitor in parallel with a low-inductance 0.1 m f ceramic capacitor. single-ended or differential input, v cm = 2.5 v figure 37 shows the single-ended configuration that gives the best sinad performance. to optimize dynamic specifications, center the common-mode voltage of the analog input at approximately by 2.5 v by connecting vinb to vref, a low- impedance 2.5 v source. as described above, shorting the sense pin directly to the refcom pin results in a 2.5 v refer ence voltage and a 5 v p-p input span. the valid range for input signals is 0 v to 5 v. the vref pin should be by- passed to the refcom pin with a 10 m f tantalum capacitor in parallel with a low inductance 0.1 m f ceramic capacitor. this reference configuration could also be used for a differential input in which vina and vinb are driven via a transformer as shown in figure 32. in this case, the common-mode voltage, v cm , is set at midsupply by connecting the transformers center tap to cml of the ad9240. vref can be configured for 1 v or 2.5 v by connecting sense to either vref or refcom respectively. note that the valid input range for each of the differential inputs is one half of the single- ended input and thus becomes v cm C vref/2 to v cm + vref/2. 0.1mf 10mf vina vinb vref sense refcom ad9240 5v 0v 2.5v figure 40. internal reference5 v p-p input span, v cm = 2.5 v resistor programmable reference figure 41 shows an example of how to generate a reference voltage other than 1 v or 2.5 v with the addition of two external resistors and a bypass capacitor. use the equation, vref = 1 v (1 + r 1/ r 2), to determine appropriate values for r1 and r2. these resistors should be in the 2 k w to 100 k w range. for the example shown, r1 equals 2.5 k w and r2 equals 5 k w . from the equa- tion above, the resultant reference voltage on the vref pin is 1.5 v. this sets the input span to be 3 v p-p. to assure stabil- ity, place a 0.1 m f ceramic capacitor in parallel with r1. the common-mode voltage can be set to vref by connecting vinb to vref to provide an input span of 0 to 2 vref. alternatively, the common-mode voltage can be set to 2.5 v by connecting vinb to a low impedance 2.5 v source. for the exam ple shown, the valid input signal range for vina is 1 v to 4 v since vinb is set to an external, low impedance 2.5 v source. the vref pin should be bypassed to the refcom pin with a 10 m f tantalum capacitor in parallel with a low induc- tance 0.1 m f ceramic capacitor. 1.5v c1 0.1mf 10mf vina vinb vref sense refcom ad9240 4v 1v 2.5v r1 2.5kv r2 5kv 0.1mf figure 41. resistor programmable reference (3 v p-p input span, v cm = 2.5 v) using an external reference using an external reference may enhance the dc performance of the ad9240 by improving drift and accuracy. figures 42 through 44 show examples of how to use an external reference with the a/d. table iii is a list of suitable voltage references from analog devices. to use an external reference, the user must disable the internal reference amplifier and drive the vref pin. connecting the sense pin to avdd disables the internal reference amplifier. table iii. suitable voltage references initial operating output drift accuracy current voltage (ppm/ 8 c) % (max) ( m a) internal 1.00 26 1.4 n/a ref191 2.048 5C25 0.1C0.5 45 internal 2.50 26 1.4 n/a ref192 2.50 5C25 0.08C0.4 45 ad780 2.50 3C7 0.04C0.2 1000 the ad9240 contains an internal reference buffer, a2 (see figure 29), that simplifies the drive requirements of an external reference. the external reference must be able to drive a ? 5 kw ( 20%) load. note that the bandwidth of the reference buffer is deliberately left small to minimize the reference noise contribu- tion. as a result, it is not possible to change the reference volt- age rapidly in this mode without the removal of the capt/ capb decoupling network, and driving these pins directly. b
ad9240 rev. C18C variable input span with v cm = 2.5 v figure 42 shows an example of the ad9240 configured for an input span of 2 vref centered at 2.5 v. an external 2.5 v reference drives the vinb pin thus setting the common-mode voltage at 2.5 v. the input span can be independently set by a voltage divider consisting of r1 and r2, which generates the vref signal. a1 buffers this resistor network and drives vref. choose this op amp based on accuracy requirements. it is essential that a minimum of a 10 m f capacitor in parallel with a 0.1 m f low inductance ceramic capacitor decouple the reference output to ground. 2.5v+vref 2.5vCvref 2.5v +5v 0.1mf 22mf vina vinb vref sense ad9240 +5v r2 0.1mf a1 r1 0.1mf 2.5v ref figure 42. external reference, v cm = 2.5 v (2.5 v on vinb, resistor divider to make vref) single-ended input with 0 to 2 3 vref range figure 43 shows an example of an external reference driving both vinb and vref. in this case, both the common mode voltage and input span are directly dependent on the value of vref. more specifically, the common-mode voltage is equal to vref while the input span is equal to 2 vref. thus, the valid input range extends from 0 to 2 vref. if, for example, the ref191, a 2.048 external reference, were selected, the valid input range extends from 0 v to 4.096 v. in this case, 1 lsb of the ad9240 corresponds to 0.250 mv. it is essential that a minimum of a 10 m f capacitor in parallel with a 0.1 m f low induc- tance ceramic capacitor decouple the reference output to ground. 2xref 0v +5v 10mf vina vinb vref sense ad9240 +5v 0.1mf vref 0.1mf 0.1mf figure 43. input range = 0 v to 2 vref low cost/power reference the external reference circuit shown in figure 44 uses a low cost 1.225 v external reference (e.g., ad580 or ad1580) along with an op amp and transistor. the 2n2222 transistor acts in conjunction with 1/2 of an op282 to provide a very low impedance drive for vinb. the selected op amp need not be a high speed op amp and may be selected based on cost, power and accuracy. 3.75v 1.25v +5v 10mf vina vinb vref sense ad9240 +5v 0.1mf 316v 1kv 0.1mf 1/2 op282 10mf 0.1mf 7.5kv ad1580 1kv 1kv 820v +5v 2n2222 1.225v figure 44. external reference using the ad1580 and low impedance buffer digital inputs and outputs digital outputs the ad9240 output data is presented in positive true straight binary for all input ranges. table iv indicates the output data formats for various input ranges regardless of the selected input range. a twos complement output data format can be created by inverting the msb. table iv. output data format input (v) condition (v) digital output otr vina C vinb < Cvref 00 0000 0000 0000 1 vina C vinb = Cvref 00 0000 0000 0000 0 vina C vinb = 0 10 0000 0000 0000 0 vina C vinb = +vref C 1 lsb 11 1111 1111 1111 0 vina C vinb 3 +vref 11 1111 1111 1111 1 out of range (otr) an out-of-range condition exists when the analog input voltage is beyond the input range of the converter. otr is a digital output that is updated along with the data output corresponding to the particular sampled analog input voltage. hence, otr has the same pipeline delay (latency) as the digital data. it is low when the analog input voltage is within the analog input range. it is high when the analog input voltage exceeds the input range as shown in figure 45. otr will remain high until the analog input returns within the input range and an- other conversion is completed. by logical anding otr with the msb and its complement, overrange high or underrange low conditions can be detected. table v is a truth table for the over/ underrange circuit in figure 46 which uses nand gates. sys- tems requiring programmable gain conditioning of the ad9240 input signal can immediately detect an out-of-range condition, thus eliminating gain selection iterations. also, otr can be used for digital offset and gain calibration. 111111 1111 1111 111111 1111 1111 111111 1111 1110 otr Cfs +fs Cfs+1/2 lsb +fs C1/2 lsb Cfs C1/2 lsb +fs C1 1/2 lsb 000000 0000 0001 000000 0000 0000 000000 0000 0000 1 0 0 0 0 1 otr data outputs figure 45. output data format b
ad9240 rev. C19C table v. out-of-range truth table otr msb analog input is 0 0 in range 0 1 in range 1 0 underrange 1 1 overrange over = 1 under = 1 msb otr msb figure 46. overrange or underrange logic digital output driver considerations (drvdd) the ad9240 output drivers can be configured to interface with +5 v or 3.3 v logic families by setting drvdd to +5 v or 3.3 v respectively. the ad9240 output drivers are sized to provide sufficient output current to drive a wide variety of logic families; large drive currents tend to cause glitches on the supplies and may affect sinad performance. applications requiring the ad9240 to drive large capacitive loads or large fanout may require additional decoupling capacitors on drvdd. in extreme cases, external buffers or latches may be required. clock input and considerations the ad9240 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. the clock input must meet or exceed the minimum specified pulsewidth high and low (t ch and t cl ) specifications for the given a/d, as defined in the switching specifications at the beginning of the data sheet, to meet the rated performance specifications. for example, the clock input to the ad9240 operating at 10 msps may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified t ch and t cl is 45 ns. for clock rates below 10 msps, the duty cycle may deviate from this range to the extent that both t ch and t cl are satisfied. all high speed high resolution a/ds are sensitive to the quality of the clock input. the degradation in snr at a given full-scale input frequency (f in ), due only to aperture jitter (t a ), can be calculated with the following equation: snr = 20 log 10 [1/(2 p f in t a ) ] in the equation, the rms aperture jitter, t a , represents the root- sum square of all the jitter sources, which include the clock input, analog input signal and a/d aperture jitter specification. for example, if a 5.0 mhz full-scale sine wave is sampled by an a/d with a total rms jitter of 15 ps, the snr performance of the a/d will be limited to 66.5 db. undersampling applications are particularly sensitive to jitter. the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9240. as such, supplies for clock drivers should be separated from the a/d output driver supplies to avoid modulating the clock signal with digital noise. low jitter crystal controlled oscil- lators make the best clock sources. if the clock is generated from another type of source (by gating, dividing or other method), it should be retimed by the original clock at the last step. most of the power dissipated by the ad9240 is from the analog power supply; however, lower clock speeds will reduce digital current slightly. figure 47 shows the relationship between power and clock rate. clock frequency C mhz 400 200 220 4 6 8 10 12141618 380 300 260 240 220 360 340 280 320 power C mw figure 47. power consumption vs. clock frequency (r bias = 2 k w ) grounding and decoupling analog and digital grounding proper grounding is essential in any high speed, high resolution system. multilayer printed circuit boards (pcbs) are recom- mended to provide optimal grounding and power schemes. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation and ground plane. these characteristics result in both a reduction of electro- magnetic interference (emi) and an overall improvement in performance. it is important to design a layout that prevents noise from coupling onto the input signal. digital signals should not be run in paral- lel with input signal traces and should be routed away from the input circuitry. while the ad9240 features separate analog and digital ground pins, it should be treated as an analog component. the avss, dvss and drvss pins must be joined together directly under the ad9240. a solid ground plane under the a/d is acceptable if the power and ground return currents are care- fully managed. alternatively, the ground plane under the a/d may contain serrations to steer currents in predictable directions where cross-coupling between analog and digital would other- wise be unavoidable. the ad9240/eb ground layout, shown in figure 57, depicts the serrated type of arrangement. the analog and digital grounds are connected by a jumper below the a/d. b
ad9240 rev. C20C analog and digital supply decoupling the ad9240 features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. frequency C khz 120 psrr C dbfs 100 1000 80 60 40 100 10 1 avdd dvdd figure 48. psrr vs. frequency figure 48 shows the power supply rejection ratio vs. frequency for a 200 mv p-p ripple applied to both avdd and dvdd. in general, avdd, the analog supply, should be decoupled to avss, the analog common, as close to the chip as physically possible. figure 49 shows the recommended decoupling for the analog supplies; 0.1 m f ceramic chip capacitors should provide adequately low impedance over a wide frequency range. note that the avdd and avss pins are co-located on the ad9240 to simplify the layout of the decoupling capacitors and provide the shortest possible pcb trace lengths. the ad9240/eb power plane layout, shown in figure 58, depicts a typical arrangement using a multilayer pcb. 0.1mf avdd avss ad9240 0.1mf avdd avss figure 49. analog supply decoupling the cml is an internal analog bias point used internally by the ad9240. this pin must be decoupled with at least a 0.1 m f capacitor as shown in figure 50. the dc level of cml is ap- proximately avdd/2. this voltage should be buffered if it is to be used for any external biasing. 0.1mf cml ad9240 figure 50. cml decoupling the digital activity on the ad9240 chip falls into two general categories: correction logic and output drivers. the internal correction logic draws relatively small surges of current, mainly during the clock transitions. the output drivers draw large current impulses while the output bits are changing. the size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. note that the internal correction logic of the ad9240 is referenced dvdd while the output drivers are referenced to drvdd. the decoupling shown in figure 51, a 0.1 m f ceramic chip capacitor, is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pf on each pin). applications involving greater digital loads should consider increasing the digital decoupling proportionally and/or using external buffers/ latches. 0.1mf dvdd dvss ad9240 drvdd drvss 0.1mf figure 51. digital supply decoupling a complete decoupling scheme will also include large tantalum or electrolytic capacitors on the pcb to reduce low-frequency ripple to negligible levels. for more information regarding the placement of decoupling capacitors, refer to the ad9240/eb schematic and layouts in figures 54C58. applications direct if down conversion using the ad9240 sampling if signals above an adcs baseband region (i.e., dc to f s /2) is becoming increasingly popular in communication applications. this process is often referred to as direct if down conversion or undersampling. there are several potential benefits in using the adc to alias (or mix) down a narrowband or wide- band if signal. first and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters reducing cost and power dissipation. second is the ability to apply various dsp techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. a detailed discussion on using this technique in digital receivers can be found in analog devices application notes an-301 and an-302. in direct if down conversion applications, one exploits the inherent sampling process of an adc in which an if signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will downconvert an if signal. similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the adcs baseband region. a tradeoff exists between the complexity of this image rejection filter and the sample rate as well as dynamic range of the adc. until recently, the actual implementation of direct if down conversion has been limited by the lack of cost-effective adcs with sufficiently wide dynamic range and high sample rates for ifs beyond 10.7 mhz. since the performance of the ad9240 in the differential mode of operation extends well beyond its baseband region, it may be well suited as a mix-down converter in narrowband as well as some wideband applications. also, with the full-power bandwidth of the ad9240 extending beyond 60 mhz, various if frequencies exist over this frequency range in which the ad9240 maintains excellent dynamic performance. figure 52 shows the ad9240 configured in an if sampling application at 37.5 mhz. to reduce the complexity of the digital demodulator in many quadrature demodulation applica- tions, the if frequency and/or sample rate are selected such that b
ad9240 rev. C21C the bandlimited if signal aliases back into the center of the adcs baseband region (i.e. f s /4). at a sample rate of 10 msps, an image of the if signal centered at 37.5 mhz will be aliased back to 2.5 mhz which corresponds to one quarter of the sample rate (i.e. f s /4). note, the if signal in this case will have undergone a frequency inversion that may easily be corrected for in the digital domain. 200v 0.1mf ad9240 vina cml vinb 50v ad8009 50v 280v 93.1v ad8009 200v 22.1v 50v saw filter output g 1 = 20db g 2 = 12db mini-circuits t4-6t figure 52. simplified ad9240 if sampling circuit to maximize its distortion performance, the ad9240 is config- ured in the differential mode using a transformer. preceding the ad9240 is a bandpass filter and a 32 db gain stage. a large gain stage may be required to compensate for the high insertion losses of a saw filter used for image rejection. the g ain stage will also provide adequate isolation for the saw filter from the transient currents associated with ad9240s input stage. the gain stage can be realized using one or two cascaded ad8009 op amps. the ad 8009 is a low cost current-feedback op amp having a third order intercept of 33 db for a gain of +10 mhz at 37.5 mhz. a passive bandpass filter is required after the ad8009 to reduce the resulting second order distortion prod- ucts and limit its out-of-band noise. the specifications of this filter are application dependent and will affect both the total distortion and noise performance of this circuit. figure 53 shows the single-tone snr and sfdr performance of the ad9240 configured in the 2 v and 5 v span without u sing the ad8009 gain stage. only a slight degradation in snr perfor- mance (i.e., 1 db) was noted with the inclusion of the ad8009 gain s tage and a bandpass filter. note, the tradeoff in snr and sfdr (dbfs) performance between the 5 v and 2 v spans at different signal levels. input power level C dbfs 40 C30 C80 C70 C60 C40 80 60 50 70 30 20 worst case spurious and snr C dbc 10 0 C50 C20 C10 0 sfdr w/5v span sfdr w/2v span snr w/5v span snr w/2v span figure 53. single-tone snr/sfdr vs. input amplitude @ 37.45 mhz figure 54 compares the two tone sfdr performance of the ad9240 in the 2 v span with and without the use of the ad8009 gain stage. no degradation in distortion performance was noted with the inclusion of the ad8009 gain stage provided that the ad8009 2nd order distortion products are sufficiently attenu- ated by the bandpass filter. input power level (f 1 = f 2 ) C dbfs 40 C90 C30 C80 C70 C60 C40 100 90 80 60 50 70 30 20 worst case spurious C dbc and dbfs 10 0 C50 C20 C10 0 w/o ad8009 C dbfs w/ad8009 C dbfs w/o ad8009 C dbc w/ad8009 C dbc 85 db reference line figure 54. two tone sfdr vs. input amplitude @ f 1 = 36.40 mhz and f 2 = 38.60 mhz b
ad9240 rev. C22C 2 3 ad817 v ee u3 a r7 1kv c16 0.1m f r8 316v a q1 2n2222 a c17 10m f 16v a c18 0.1m f r6 820v +5va tp25 r4 50v jp10 r3 15kv a c12 0.1m f a r5 10kv c13 10m f 16v a v in v out gnd ref43 a external reference drive u2 v cc c14 0.1m f 6 7 4 v cc a c15 0.1m f 74hc541n tpd c19 0.1m f 6 7 2 3 4 v cc ad845 a c21 0.1m f v ee u4 a r11 500v c20 0.1m f a r14 10kv a cw r13 10kv buffer jp23 r10 500v 1 2 3 a b jp24 direct couple option c38 ac couple option jp14 jp13 a r9 50v a j1 vin r12 33v r15 33v +5va a d2 1n5711 d1 1n5711 ac couple option +5va a d4 1n5711 d3 1n5711 r39 2 j8 4j8 6 j8 8 j8 10 j8 12 j8 14 j8 16 j8 18 j8 20 j8 22 j8 24 j8 26 j8 39 j8 28 j8 29 j8 30 j8 31 j8 32 j8 34 j8 35 j8 36 j8 37 j8 38 j8 nc nc nc +5va u8 decoupling a 11 10 u8 98 u8 34 u8 1 2 u8 13 12 u8 a +5vd u5 decoupling 5 6 u5 12 u5 3 4 u5 spare gates jp18 jp17 r20 22.1v 13 j8 tp10 r21 22.1v 11 j8 tp11 r22 22.1v 9 j8 tp12 r23 22.1v 7j8 tp13 r24 22.1v 5 j8 tp14 r25 22.1v 3 j8 tp15 r26 22.1v 1 j8 tp16 r27 22.1v 33 j8 tp3 r28 22.1v 27 j8 tp4 r29 22.1v 25 j8 tp5 r30 22.1v 23 j8 tp17 r31 22.1v 21 j8 tp6 r32 22.1v 19 j8 tp7 r33 22.1v 17 j8 tp8 r34 22.1v 15 j8 tp9 c24 0.1m f +drvdd 74hc541n 20 a j9 clkin u5 13 12 u5 98 jp15 clkb jp16 clk u5 11 10 u8 65 c23 0.1m f tp2 a r19 50v r40 r41 a r16 5kv +5va r18 5kv r17 1kv cw d13 adc_clk y7 y6 y5 y4 y3 y2 y1 y0 +5vd u6 g1 g2 a7 a6 a5 a4 a3 a2 a1 a0 gnd +drvdd 20 y7 y6 y5 y4 y3 y2 y1 y0 +5vd u7 g1 g2 a7 a6 a5 a4 a3 a2 a1 a0 gnd bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 otr vref sense refcom capt capb cml vina vinb u1 ad9240mqfp avdd2 32 31 33 37 36 39 41 42 28 42 29 tp24 c8 0.1m f a a jp7 +5va c9 0.1m f a 25 24 d13 23 d12 22 d11 21 d10 20 d9 19 d8 18 d7 17 d6 16 d5 15 d4 14 d3 13 d2 12 d1 11 d0 5 7 c43 0.1m f c10 0.1m f c11 0.1m f +drvdd c2 0.1m f + c1 10m f 16v a jp6 jp3 +5va jp4 jp5 r1 10kv r2 10kv a c41 0.1m f jp2 tpc tpd a c6 0.1m f + c5 10m f 16v c3 0.1m f c4 0.1m f a cml a vina2 vina1 jp11 b a 321 vinb2 vinb1 jp12 b a 321 jp8 +5vd a drvss dvss drvdd dvdd tp1 1 63 clk c7 0.1 m f avdd1 avss2 avss1 adc_clk t1 6 5 4 1 2 3 pri sec r36 200v a c36 15pf r37 33v r38 33v vina1 vinb1 a c37 15pf jp21 tpc jp22 tpd jp1 cml r35 50v a a j10 ain a tp26 sj6 40 j8 a a + c28 22m f 25v c32 0.1m f l1 tp18 j2 +5a a a + c29 22m f 25v c33 0.1m f l2 tp19 j3 +5d a a + c30 22m f 25v c34 0.1m f l3 tp20 j4 +v cc a a + c31 22m f 25v c35 0.1m f l4 tp21 j5 Cv ee + c39 22m f 25v c40 0.1m f l5 tp27 j11 +5_or _+3 +drvdd v ee v cc +5vd +5va j6 tp23 j7 a jg1-wire etch ckt side 5 sets of pads to connect grounds jg1 sj1 sj2 sj3 sj4 sj5 agnd dgnd tp22 vina2 vinb2 tpd tpc 74hc14 74hc04 d7 9 d8 8 d9 7 d10 6 d11 5 d12 4 d13 3 2 10 19 1 11 12 13 14 15 16 17 18 11 12 13 14 15 16 17 18 clk 9 d0 8 d1 7 d2 6 d3 5 d4 4 d5 3 10 19 1 c25 0.1m f c22 0.1m f c26 0.1m f c42 0.1m f bias 35 r bias d6 2 figure 55. evaluation board schematic b
ad9240 rev. C23C figure 56. evaluation board component side layout (not to scale) figure 57. evaluation board solder side layout (not to scale) figure 58. evaluation board ground plane layout (not to scale) figure 59. evaluation board power plane layout (not to scale) b
ad9240 rev. b | page 24 of 24 outline dimensions compliant to jedec standards ms-022-ab-1 041807-a 13.45 13.20 sq 12.95 0.45 0.29 2.45 max 1.03 0.88 0.73 top view (pins down) 12 44 1 22 23 34 33 11 0.25 0.10 2.20 2.00 1.80 7 0 view a rotated 90 ccw 0.23 0.11 10.20 10.00 sq 9.80 0.80 bsc lead pitch lead width 0.10 coplanarity v i e w a s e a t i n g p l a n e 1 . 6 0 r e f pin 1 figure 1. 44-lead metric quad flat package [mqfp] (s-44-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9240as ?55c to +85c 44-lead mqfp s-44-1 ad9240asrl ?55c to +85c 44-lead mqfp s-44-1 AD9240ASZ ?55c to +85c 44-lead mqfp s-44-1 AD9240ASZrl ?55c to +85c 44-lead mqfp s-44-1 1 z = rohs compliant part. ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08985-0-3/10(b)

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